Extended aperture deltic correlator

ABSTRACT

There are disclosed arrangements for extending the aperture of Deltic correlators which involve (1) cascading the delay line loops each of which has a time delay approximately equal to the maximum sampling period, and (2) increasing the sampling period by making it a multiple of the basic sample period.

O7- O 71 XR 39591.9789

United btates Patent 1 1 3,591,789

[72] Inventors David Hoffman [56] References Cited UNITED STATES PATENTS$2? Budd 3,424,899 1/1969 Dunnican et al 235/181 ams,Spnngi1eld, Va.

3,479,495 11/1969 Malm 235/181 793941 3 488 635 1 1970 Sff 1 235 181 x[22] Filed Jam 22,1969 l 1 er en [45] Patented July 6, 1971 OTHERREFERENCES [731 Assignee The United States of America as Allen et al.:Digital Compressed-Time Correlators and represented by the Secretary ofthe Navy Matched Filters for Active SONAR," JOURNAL OF THE ACOUSTlCALSOC. 0F AM., Vol. 36 No. 1 Lan. 1964 p. 121- 139 Scient. Lib. QC221 A-4s4 EXTENDED APERTURE DELTIC CORRELATOR 'i 'F MOmSO" 3 Claims, 2 DrawingFigs Assistant Examiner-Felix D. Gruber Attorneys-R. l. Tompkins and L.I. Shrago I52] U.S. Cl 235/181,

235/150.53, 324/77 H, 325/38 B, 325/323, M 340/173 ABSTRACT: There aredisclosed arrangements for extending [51] Int. Cl ..G06f 15/34, theaperture of Deltic correlators which involve (1) cascading 606g 7/19 thedelay line loops each of which has a time delay approxi- [50] Field ofSearch 235/181, mately equal to the maximum sampling period, and (2) in-150.5, 150.5 340/173, 15.5; 324/77 H, 77 B; creasing the sampling periodby making it a multiple of the 343/1007; 325/38 B basic sample period.

I- DELT/c (043544701 2 0527/: Cokeaafa Paras: M Perccsswa (wa /rPATENTED JUL 6 1971 SHEET 1 [1F 2 EXTENDED APERTURE lDlElL'l'llCCORRELATOR The invention described herein may be manufactured and usedby or for the Government of the United States of Amer ica forgovernmental purposes without the payment of any royalties thereon ortherefor.

The present invention relates generally to Deltic correlators and, moreparticularly, to arrangements for and methods of extending the apertureof these correlators beyond the limits previously imposed on the systemby the finite length and operating frequency of the delay apparatus;

in a standard correlator, digital techniques are usually used todetermine the correlation function given by the expression where f(t)signal being processed g(t) replica of signal T= length of replica(aperture) Thus, the signal being processed must be multiplied by itsreplica or the reference signal and integrated for each value of thetime delay.

in the Deltic correlator, the signal being processed,f(t), is hardclipped and periodically sampled before being applied to the input of adelay line that has the capacity of being able to store sequentially Dlbits, where D is the number of bits the delay apparatus could store ifits time delay were equal to the sampling period. The output of thedelay apparatus is fed back to the input through an inhibiting circuitwhich prevents recirculation of this signal when a sampling pulse ispresent. Since the of the delay apparatus in real time is one bit timeless than the sampling period, the first sample loaded into the linetravels down the line, is fed back to the input and travels back downthe line for one bit time before the next sample occurs and enters theline. For each subsequent sample, the process is repeated with the lastsample being loaded into the line one bit time following the precedingsample until the line is filled with D] bits. The first sample has nowprecessed down the line by Dl bit times. When the next sampling pulseoccurs, this precession amounts to D bits and the first sample istherefore in time coincidence with this sampling pulse. Recirculation ofthis first sample is consequently rejected in the inhibiting circuit andits place in the delay line storage apparatus taken by the Dth signalsample. This mode of operations is continued with each succeeding signalsample replacing the oldest sample then stored in the delay line.

At the output of the delay line, starting at the time of the Dthsampling pulse, there appears a pulse train corresponding to the sampleversion of f(t), the signal being processed but compressed in time toone sample period. During each ensuing period, the pulse train ispresented to the output but each time it is shifted in time by onesample period.

The arrangement for storing the replica of the signal g(t) or areference signal operates in essentially the same manner for D samplepulses. At this time, the Dl most recent samples are sequentially storedin the delay line but the oldest sample, which is prevented fromreentering the delay line, is not dropped but stored in a one-bit shiftregister which is clocked at a rate equal to the bit rate or operatingfrequency of the delay line. Thereafter, the feedback loop includes thisregister, and the output of this new loop is a sample time-compressedversion of 3(1), repeating itself once a sampling period. Consequently,the output of the reference storage is a stationary time series of bitscorresponding to a sampled time-compressed version ofg(l).

In the correlator, the time-compressed signal f(t) and replica g(t) aremultiplied together, and the resultant serves as the input to anintegrator whose output is the desired correlation function.

The delay line in the Deltic correlator, it will be appreciated,accomplishes two purposes, namely, it time compresses the signal beingprocessed, f(!), so that a repeat correlation with a replica, g(r), canbe performed, and it provides the means for obtaining f(I)'T byrepresenting a signal delayed progressively in increments equal to thesampling period.

The number of samples that can be stored in the delay line is dependenton the length of this line and the minimum time spacing between storedsamples that the frequency response of the line will permit. The delayof the line cannot exceed the maximum allowable sampling period less onesample spacing. Thus, the duration of the real time signal that can bestored becomes limited by the number of samples that can be accommodatedin a line having that length.

in the 'standard Deltic correlator, the electrical specifications of thedelay line, as mentioned above, are determined by two main parameters,the period T, ofthe sampling pulses s(t) and the duration Tof real timesignal to be compared against a reference or replica signal of the samelength for various values of r. The electrical length of both the signaland replica delay lines is equal to T, (minus one bit time for the caseof the f(!) signal line which will be neglected for the purpose of thisdiscussion). The number of bits or samples that must be stored in a lineis equal to the ratio T/T,. The operation frequency of the delay line(1",) is equal to the number of stored bits divided by its length orTIT}.

In many cases, especially when the correlator is to be used for signalenhancement, it is advantageous to make T, the aperture of thecorrelator, as large as possible. Since T=7,,Tf, the technique is to useas large a sampling period as is permitted by the bandwidth of thesignal and to operate the line at its maximum reliable frequency. if,however, the sampling rate cannot be reduced because of otherconsiderations and the storage cannot be made to circulate any faster,the aperture cannot be extended in the conventional circuit.

Referring again to the expression,

the correlation function, the aperture in real time is T. If theaperture is increased by a factor of N, then equation (1) becomes Thisnew integral can be broken up into N parts resulting in It will be seenthat the first integral in the brackets is exactly of the same form asbefore aperture extension. The second integral is the same exceptintegration is performed from T to 2T. All subsequent integrals are alsothe same with the exception that the location of the integrationinterval progresses in real time.

From a study of the summed integrals, it may be seen that the apertureof a recirculating delay line correlator operating at a given samplingrate may be increased in the following manner: N correlator sections,each equivalent in length to the sampling interval, may be employed. Thereference and signal lines in each section store a part of the signaland replica T seconds long in real time. Each part of the replica andsignal are allowed to recirculate in each individual loop section wherethey are stored. This permits multiplication of the part of the replicaand signal associated with each interval of integration. For a givenvalue of r, the signal is also split up into the individualrecirculating signal lines. However, after each recirculation, a 1-shift of one bit is achieved in each line by dumping out its oldest bitinto a line that is performing integration in the succeeding integrationtime interval. The individual section performing integration between 0and T has its signal line updated each recirculation period by theoldest bit from the Tto 2 Tsection. It, in turn, discards its oldestbit. The component which integrates from (N-l )T to T is updated by thelatest sample of the signal being analyzed. Multiplication andintegration of the signal and replica outputs of each individual lineare performed as in a conventional correlator, and the summation yieldsp ('r).

It is, accordingly, a primary object of the present invention to providea Deltic correlator ofincreased aperture.

Another object of the present invention is to provide a Delticcorrelator wherein the aperture is extended without increasing the delayline length.

Another object of the present invention is to provide a Delticcorrelator utilizing interconnected delay lines, each of which has atime delay approximately equal to the basic sampling period.

Another object of the present invention is to provide a Delticcorrelator whose sampling period is a multiple of the basic samplingfrequency.

Other objects, advantages and novel features of the invention willbecome apparent from the following detailed description of the inventionwhen considered in conjunction with the accompanying drawings wherein:

FIG. 1 is a schematic drawing of a cascaded Deltic correlatorarrangement embodying one form of the present invention wherein theaperture is increased by a factor of two; and

FIG. 2 illustrates an arrangement for use in the Deltic correlator forextending the sampling period by multiples of the basic samplingfrequency.

Referring to FIG. 1 of the drawings, the arrangement illustratedconsists of a pair of cascaded Deltic correlators which cooperate toprovide an aperture twice the length of that of each correlator in thesystem. Each correlator has an input signal processing circuit in theupper portion thereof and a replica or reference signal processingcircuit in the lower portion thereof.

The input signalf(t), which may be a binary signal obtained from asuitable source 10, is fed first to a clipper 11 which hard clips thissignal and then is sent to a gate 12 controlled by sampling pulses.s-(t) from a suitable source 13. Each sample of signal f(t) is fed to adelay line 14 whose length is T,Xl bit times long. The output of delayline 14 is fed back to its input through a gate 15 also controlled bysampling pulses obtained from source 13.

The operation of this portion of the Deltic correlator has beendescribed hereinbefore in general terms. Each sample enters the delayline through gate 12 and is stacked one bit time apart because of thelength of delay line 14 with respect to T,,, the period of samplingpulses 13. When the line is filled with Dl bits, the first sample in thenext cycle appears at gate 15 in time coincidence with a sampling pulse.Gate 15 inhibits the circulation of this first sample. It isconsequently rejected from the system and a new sample is fed into thedelay line through gate 12 to replace it. Thereafter, each newsucceeding sample replaces the oldest sample and, at the output of delayline 14, there appears a pulse train corresponding to the sampledversion of f(t) but compressed in time to one sample period, T,,. Theoutput of delay line 14 in the first correlator goes to a one bitregister 16 which is controlled by sampling pulses from source 13. Thisregister is coupled to a gate 17 also controlled by sampling pulses fromthis same source. Connected to this gate is a second delay line 18having a time delay equal to delay line 14. This delay line, too, has afeedback path through a gate 19 controlled by sampling pulses.

In the operation of the input signal processing circuit, when a sampleis discarded from delay line 14 by the inhibiting action of gate 15,this same sample enters register 16 and thereafter passes into delayline 18 of the second Deltic correlator when the next sampling pulseoccurs. Thus, each successive oldest sample from the first correlator isselected from the compressed pulse train in successive cycles and entersthe delay line in intervals T, duplicating the loading of delay line 14in the first Deltic correlator. This loading continues with each samplenow being stacked in delay line 18 during successive recirculationsthrough gate 19 until the oldest of these samples appears at this gatein time coincidence with a sampling pulse from source 13. Thisparticular sample is now rejected by the gate and a new sample entersthe loop through gate 17 from the first correlator. The rejected sampleenters register 20, and this register controlled by sample pulsesprovides an output which may be used in a third cascaded, Delticcorrelator, if desired. In such a case, it would be followed by gatessimilar to 17 and 19 and a third delay line.

From what has been described hereinbefore, it will be appreciated thatthe input signal processing circuit accommodates two D bit of the inputsample. The first D bits are in the second correlator in delay line 18,having a capacity of D-l, and register 20 having a l-bit capacity.Likewise, the second D bits are in the first correlator in delay line 14and register 16. As the system operates, the oldest of these bits orsamples is dropped out of the system at the output of register 20 of thesecond correlator and a replacement for this sample enters the firstcorrelator, representing a new portion of the input signal. Thus, twicethe length of the input signal which could be accommodated in one of theDeltic correlators progresses through the cascaded arrangement.

Turning now to the reference signal processing circuit of the system, areference signal g(z) obtained from a suitable source 30 is fed first toa clipper 21 which hard clips it and then to a gate 32 controlled bysampling plus s(t) from source 33. Gate 32 is also controlled by longpulses obtained from a source 38. These pulses, when present at gate 32,effectively block the gate and prevent samples of the reference signalfrom entering the system. Each sample of signal g(t) is fed to a delayline 34 whose length equals that of delay line 14 in the signalprocessing circuit. The output ofdelay line 34 is fed back to its inputthrough a first loop which contains a gate 35. This gate is controlledby sampling pulses from source 33 and is also controlled by a shortpulse from source 37. When a short pulse is present, gate 35 is openedand the samples of g(t) circulate around the first loop and are properlystacked, duplicating the performance of delay line 14 and gate 15 in thesignal processing circuit.

The output of delay line 34 is applied to a single bit register 39clocked at the bit rate or the operating frequencyf, of the delay lines.This register is included in a second feedback loop of delay line 34which contains a gate 36 controlled by a long pulse from source 38.

In the operation of a conventional Deltic correlator, the input signalis progressively shifted through the input signal processing circuit byfinite amounts corresponding to a sampling period during the correlationoperation, but the replica or reference signal remains, in effect,stationary in the reference signal processing circuit. The second loop,mentioned above, is closed when it is desired to render stationary thatportion of the reference signal which is accommodated within the firstDeltic correlator of the cascaded pair.

Register 39 is connected to a gate 40 which is controlled by samplingpulses from a suitable source 41 and also controlled by a long pulsefrom source 36. Connected to this gate is a delay line 43 similar to theother delay lines hereinbefore described. This delay line, like itscounterpart in the first Deltic correlator, has a first feedback loopwhich contains a gate 44 and a second feedback loop which includes aregister 47 and a gate 45. Gate 44 is also controlled by short pulsesfrom source 42, while gate 45 is controlled by long pulses from source46. i

In the operation of the reference signal processing circuit, samples ofthe reference signal enter delay line 34 through gate 32 and circulatethrough the first loop containing gate 35 until 0-] bits are in delayline 34. In the next cycle, it will be appreciated, gate 35 duplicatesthe performance of gate 15, rejecting the oldest bit and allowing a newsample to enter the loop through gate 32.

This oldest sample enters register 39 and subsequently passes into delayline 43 through gate 40 in a manner similar to that previously describedin connection with the signal processing circuit. The pulses which soenter delay line l3 from the first correlator are stacked in the propersequence and, when Dl bits are in delay line 43, gate 44 acts to removethe oldest sample and allow a new sample to enter the line through gate40. However, this oldest sample is now in register 47 and may be sent toa third cascaded Deltic correlator if desired.

When two D pulses are present in the reference signal processingcircuit, that is, when delay line 43 and register 47 of the secondcorrelator and delay line 34 and register 39 of the first correlator arefilled, gates Ml and are blocked by the termination of the short pulsesfrom sources 42 and 37 and gates 45 and 36 opened by the appearance ofthe long pulses from sources 46 and 38. Likewise, at this same time,gates and 32 are blocked by long pulses so that the second correlator isisolated from the first correlator and the first correlator isdisconnected from the reference signal source 30. As a result of thisswitching action, the D bils present in the second correlator now remainstationary in their second loop, completing a circulation through delayline 43, register 47 and gate once each sampling period T,,. And, by thesame token, the D bits present in the first Deltic correlator remainstationary, completing a circulation through delay line 34, register 39and gate 36 once each same sampling period. Consequently, the cascadedsystem accommodates two D bits of the reference signal, twice the numbernormally handled by a single Deltic correlator, and these two D bitsappear, in effect, as a stationary compressed series corresponding to anextended length of the reference signal.

It should be understood that a third or fourth Deltic correlator may becascaded to the system for further extending the aperture. Also,different portions of the reference signal may be selected forcorrelation by simply controlling the application of the long pulses togates 32, 36, 40 and 45. Until these gates are blocked, the referencesignal, like the input signal, will progress through the referencesignal processing circuit and the selection can be made wheneverdesired.

The time-compressed input signals appearing in the output of delay lineM are multiplied by those appearing in the out put of register 39 in anappropriate multiplication circuit 4@. This may be done in a mutuallyexclusive AND" circuit arrangement. The results of this multiplicationare integrated in circuit 50.

In the same manner, the time-compressed input signals appearing in theoutput of delay line 18 and those appearing in the output of register 47are also multiplied in circuit 511 and then integrated in circuit 52.The outputs of both integrators are added in circuit 53 to provide thedesired correlation func' tion p(r).

It would be pointed out that the reason for adding the registers l6 and20 in the signal processing circuit is to compen sate for the registersneeded in the reference signal processing circuit. If it were not forthe extra bit of storage provided by register 16, for example, the firstbit out of the signal processing circuit of the first correlator wouldbe the Dth bit, while that coming out of the reference signal processingcircuit of the same correlator would be the DXlth bit corresponding to a1' shift of 1-bit. The register remedies this situation.

In Figure 2 there is illustrated a technique for effectively increasingthe sampling period of the Deltic correlator without resorting tounreasonably long delay lines. This system may be employed to obtainsample periods which are integral multiples of the basic delay linelength. In the cascaded correlator previously described, the sampleperiod, T,,, was equal to the number ofbit times accommodated withineach delay line plus l-bit time. This extra bit time, it will berecalled, allowed the contents of the line to precess by one sample foreach circula tion. In the arrangement of FIG. 2 a provision is includedwhich prevents the delay line contents from precessing on everycirculation. It is therefore possible with this mode of operation toload samples at intervals that are multiples ofthe basic sample period,T

For a sample period ofkT the apparent length of the delay line must bekDl bit times, where k corresponds to any integer, l, 2, 3, etc. In thecircuit of FIG. 2, there are two feedback paths around the delay linewhich are rendered effective during mutually exclusive periods of time.During each extended sample interval, the contents of the delay linefirst circulates k-l times around the long feedback path which in cludesregister 61 and control gate 62. Thereafter, it circulates once aroundthe short feedback loop including gate 63. This is accomplished byapplying a first long pulse to gate 62 for the requisite time related toK and then a short pulse from source 65 to gate 63.

Since the long feedback loop includes register fill, this loop is D bittimes long. With the recirculating feature, it increases to k-l times Dbit times long. The short loop is only l -l bit times long. Thus, theeffective line length is equal to (kl) D (D bit times. This quantitysimplifies to kD- l bit times. The aperture for a correlator operatingin the mode described above will therefore be T=kf T, again showing anincrease by a factor k as compared to the basic Deltic correlator. Thismethod of extension is advantageous, as mentioned above, when thedesired sample period would otherwise dictate excessively long delaylines.

It should be appreciated that the two features hereinbefore describedmay be advantageously combined in the same system to provide an apertureextension which is the product of N and k, for example, T=Nkf,,T, Thevalues of both N and k have no theoretical limit. However, enlarging thevalue of k involves a corresponding increase in the sampling periodwhose upper limit is set by the bandwidth of the signals to beprocessed.

Although the invention has been discussed in terms of recirculatingdelay lines which store only two levels of the input signal, if thestorage apparatus does hold more levels, the same restrictions areapplicable to the standard correlator and may be overcome with thecascaded arrangement described. The multiplication algorithm must bechanged to one appropriate to the storage medium, be it digital oranalog.

One major advantage of the cascaded arrangement resides in the fact thatthe extension is accomplished without regard to improvements in thestorage medium operating frequency or length. Also, since long, highfrequency delay lines are not only expensive but unstable, with thesecond feature of the invention, a number of shorter, lower frequencylines may be employed to obtain the same aperture. Thus, one achievesmore dependable operation at a lower cost. Also, the present inventionprovides a degree of flexibility missing in previous correlators since,in the standard correlator, the delay line is a fixed piece of apparatuswhich must be reconstructed for each different application. The presentinvention allows a large, multipurpose correlator to be constructed outof subsections where the individual units may be cascaded to provide anydesired length of aperture or used as separate or groups of separatecorrelators to provide multichannel capability. Also, a failure of onesection decreases the maximum aperture by UN instead of resulting in thecomplete breakdown of the system.

It should be appreciated that the invention may employ any type ofsignal storage medium in which the information is cyclically availableincluding, for example, magnetic drums, shift registers, cores,magnetostrictive delay lines and acoustic delay lines. Furthermore, ifthe storage medium is inherently multilevel or is capable of beingemployed in this fashion, the same advantages still accrue. Formultilevel or analog operation, the 1 bit or one digit storage need onlybe made appropriate and the multiplication algorithm changed to onefitting true multilevel or analog multiplication.

What we claim is:

I. A system of cascaded Deltic correlators having an aperture ofincreased size comprising, in combination,

a first and second Deltic correlator,

each Deltic correlator having a first delay line, a first gate connectedto the input of said first delay line, a second gate connected in afirst feedback circuit of said delay line, and a first l-bit registerconnected to the output of said first delay line,

each Deltic correlator also having a second delay line, a third gateconnected to the input of said second delay line, a fourth gateconnected in a first feedback circuit of said second delay line, asecond l-bit register connected to the output of said second delay line,and a fifth gate in series with said second register in a secondfeedback circuit of said second delay line,

each Deltic correlator also having means for coupling sampling pulses tothe first, second, third, fourth gates so as to periodically open eachfirst and third gate and close each second and fourth gate;

means for connecting the output of the first l-bit register of saidfirst Deltic correlator to the first gate of said second Delticcorrelator;

said first Deltic correlator;

means for also coupling sampling pulses to the first 1-bit register ofsaid first Deltic correlator so as to periodically transfer the countstored therein to the first gate of said second Deltic correlator as aninput signal to this Deltic correlator, each of said delay lines havinga time delay slightly shorter than the time interval between samplingpulses, whereby pulse length portions of said binary input signal arefed into the first delay line of said first Deltic correlator with eachof these pulses thereafter circulating around its first feedback pathuntil a particular pulse coincides with a sampling pulse at said secondgate, each of these pulses also passing into the first register of saidfirst Deltic correlator and then, at the time of occurrence of the nextsampling pulse, through the first gate of said second Deltic correlatorinto the first delay line of said second Deltic correlator andthereafter circulating around its first feedback until a particularpulse coincides with the appearance of a sampling pulse at the firstgate ofsaid second Deltic correlator, said pulses being time compressedbecause of the length of the delay lines compared to the time intervalbetween sampling pulses whereby complementary time compressed inputsignal pulse trains representing adjacent portions of said input signalappear in the output of the first delay lines of said Delticcorrelators; means for connecting a reference signal to the third gateof said first Deltic correlator; means for connecting the output of thesecond l-bit register of said first Deltic correlator to the first gateof said second Deltic correlator; means for additionally controlling theoperation of the third, fourth and fifth gates and said second l-bitregisters such that either a first mode of operation is obtained whereinthe time compressed reference signal pulse trains which appear in theoutput of the second delay of said Deltic correlators represent the sameadjacent portions of said reference signal or a second mode of operationis obtained wherein these signal pulse trains represent changingadjacent portions of said reference signal, each Deltic correlator alsohaving means for multiplying the time compressed pulse trains appearingin the output of its first and second delay lines and for integratingthe results thereof to obtain an output signal whose amplitude isindicative of the correlation between those portions of the input andreference signal which are represented by these pulse trains; and meansfor combining the output signals from each Deltic correlator to give anoverall output signal for the cascaded system. 2. In an arrangement asdefined in claim 1 wherein said means for controlling the operation ofsaid second l-bit registers comprises a source of clock pulses coupledto said registers and having a frequency corresponding to the timeinterval between the time compressed reference signal pulses appearingin the output of the second delay lines of said first and second Delticcorrelators.

3. 1n an arrangement as defined in claim I wherein said means foradditionally controlling the operation of each third, fourth and fifthgate includes a source of relatively short pulses coupled to the fourthgates for maintaining these gates open and a source of relatively longpulses coupled to the third and fifth gates for maintaining the thirdgates open and the fifth gates closed, whereby whenever said third andfourth gates are open, pulse samples of said reference signal may be fedinto the second delay line of said first Deltic correlator and circulatearound its first feedback path and the output from the second l-bitregister in the second feedback circuit of this delay line may be fedinto the second delay line of said second Deltic correlator andcirculate around its first feedback path to produce said second mode ofoperation, and

whenever said third and fourth gates are closed and said fifth gatesopen, pulse samples of said reference signal cannot be fed into thesecond delay line of said first Deltic correlator nor can the output ofthe second l-bit register that is connected in its output circuit be fedto the second delay line of said second Deltic correlator so that thetime compressed reference signal pulse trains in the output of saidsecond delay lines circulate around the second feedback path of thesedelay lines to produce said first mode of operation.

1. A system of cascaded Deltic correlators having an aperture ofincreased size comprising, in combination, a first and second Delticcorrelator, each Deltic correlator having a first delay line, a firstgate connected to the input of said first delay line, a second gateconnected in a first feedback circuit of said delay line, and a first1-bit register connected to the output of said first delay line, eachDeltic correlator also having a second delay line, a third gateconnected to the input of said second delay line, a fourth gateconnected in a first feedback circuit of said second delay line, asecond 1-bit register connected to the output of said second delay line,and a fifth gate in series with said second register in a secondfeedback circuit of said second delay line, each Deltic correlator alsohaving means for coupling sampling pulses to the first, second, third,fourth gates so as to periodically open each first and third gate andclose each second and fourth gate; means for connecting the output ofthe first 1-bit register of said first Deltic correlator to the firstgate of said second Deltic correlator; means for coupling a binary inputsignal to the first gate of said first Deltic correlator; means for alsocoupling sampling pulses to the first 1-bit register of said firstDeltic correlator so as to periodically transfer the count storedtherein to the first gate of said second Deltic correlator as an inputsignal to this Deltic correlator, each of said delay lines having a timedelay slightly shorter than the time interval between sampling pulses,whereby pulse length portions of said binary input signal are fed intothe first delay line of said first Deltic correlator with each of thesepulses thereafter circulating around its first feedback path until aparticular pulse coincides with a sampling pulse at said second gate,each of these pulses also passing into the first register of said firstDeltic correlator and then, at the time of occurrence of the nextsampling pulse, through the first gate of said second Deltic correlatorinto the first delay line of said second Deltic correlator andthereafter circulating around its first feedback until a particularpulse coincides with the appearance of a sampling pulse at the firstgate of said second Deltic correlator, said pulses being time compressedbecause of the length of the delay lines compared to the time intervalbetween sampling pulses whereby complementary time compressed inputsignal pulse trains representing adjacent portions of said input signalappear in the output of the first delay lines of said Delticcorrelators; means for connecting a reference signal to the third gateof said first Deltic correlator; means for connecting the output of thesecond 1-bit register of said first Deltic correlator to the first gateof said second Deltic correlator; means for additionally controlling theoperation of the third, fourth and fifth gates and said second 1-bitregisters such that either a first mode of operation is obtained whereinthe time compressed reference signal pulse trains which appear in theoutput of the second delay of said Deltic correlators represent the sameadjacent portions of said reference signal or a second mode of operationis obtained wherein these signal pulse trains represent changingadjacent portions of said reference signal, each Deltic correlator alsohaving means for multiplying the time compressed pulse trains appearingin the output of its first and second delay lines and for integratingthe results thereof to obtain an output signal whose amplitude isindicative of the correlation between those portions of the input andreference signal which are represented by these pulse trains; and meansfor combining the output signals from each Deltic correlator to give anoverall output signal for the cascaded system.
 2. In an arrangement asdefined in claim 1 wherein said means for controlling the operation ofsaid second 1-bit registers comprises a source of clock pulses coupledto said registers and having a frequency corresponding to the timeinterval between the time compressed reference signal pulses appearingin the output of the second delay lines of said first and second Delticcorrelators.
 3. In an arrangement as defined in claim 1 wherein saidmeans for additionally controlling the operation of each third, fourthand fifth gate includes a source of relatively short pulses coupled tothe fourth gates for maintaining these gates open and a source ofrelatively long pulses coupled to the third and fifth gates formaintaining the third gates open and the fifth gates closed, wherebywhenever said third and fourth gates are open, pulse samples of saidreference signal may be fed into the second delay line of said firstDeltic correlator and circulate around its first feedback path and theoutput from the second 1-bit register in the second feedback circuit ofthis delay line may be fed into the second delay line of said seconDDeltic correlator and circulate around its first feedback path toproduce said second mode of operation, and whenever said third andfourth gates are closed and said fifth gates open, pulse samples of saidreference signal cannot be fed into the second delay line of said firstDeltic correlator nor can the output of the second 1-bit register thatis connected in its output circuit be fed to the second delay line ofsaid second Deltic correlator so that the time compressed referencesignal pulse trains in the output of said second delay lines circulatearound the second feedback path of these delay lines to produce saidfirst mode of operation.